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PRELIMINARY
FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
ICS844001-21
GENERAL DESCRIPTION
The ICS844001-21 is a a highly versatile, low IC S phase noise LVDS Synthesizer which can generate HiPerClockSTM low jitter reference clocks for a var iety of communications applications and is a member of the HiPerClocksTM family of high performance clock solutions from IDT. The dual crystal interface allows the synthesizer to support up to two communications standards in a given application (i.e. 1GB Ethernet with a 25MHz crystal and 1Gb Fibre Channel using a 25.5625MHz crystal). The rms phase jitter performance is typically less than 1ps, thus making the device acceptable for use in demanding applications such as OC48 SONET and 10Gb Ethernet. The ICS844001-21 is packaged in a small 24-pin TSSOP package.
FEATURES
* One differential LVDS output pair and one LVCMOS reference output * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * VCO range: 560MHz - 700MHz * Supports the following applications: SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV * RMS phase jitter @ 622.08MHz (12kHz - 20MHz): 0.92ps (typical) * Full 3.3V supply mode * 0C to 70C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
BLOCK DIAGRAM
3 N2:N0 SEL0 Pulldown SEL1 Pulldown N XTAL_IN0 000 001 010 011 100 101 110 111 /1 /2 /3 /4 (default) /5 /6 /8 /10
PIN ASSIGNMENT
VDDO_CMOS N0 N1 N2 VDDO_LVDS Q0 Q nQ0 GND nQ VDDA VDD XTAL_OUT1 XTAL_IN1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 REF_OUT GND REF_OE M2 M1 M0 MR SEL1 SEL0 REF_CLK XTAL_IN0 XTAL_OUT0
OSC
XTAL_OUT0 XTAL_IN1
00
11
OSC
XTAL_OUT1 REF_CLK Pulldown
01
Phase Detector
VCO
10 01 00
10 11
000 001 010 011 100 101 110 111
M /18 /22 /24 /25 /32 (default) /40 /40 /40
ICS844001-21
24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View
MR Pulldown M2:M0 3
REF_OUT REF_OE Pulldown
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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ICS844001AG-21 REV. A SEPTEMBER 14, 2007
ICS844001-21 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 3 4 5 6, 7 8, 23 9 10 11 12 13 14 15 16, 17 18 19, 20 21 22 24 Name VDDO_CMOS N0, N1 N2 VDDO_LVDS Q, nQ GND VDDA VDD XTAL_OUT1, XTAL_IN1 XTAL_OUT0, XTAL_IN0 REF_CLK SEL0, SEL1 MR M0, M1 M2 REF_OE REF_OUT Input Input Power Ouput Power Power Power Input Input Input Input Input Input Input Input Output Type Power Pullup Description Output supply pin for LVCMOS output. Output divider select pins. Default /4. LVCMOS/LVTTL interface levels. Pulldown Output supply pin for LVDS outputs. Differential output pair. LVDS interface levels. Power supply ground. Analog supply pin. Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT1 is the output, XTAL_IN1 is the input. Parallel resonant cr ystal interface. XTAL_OUT0 is the output, XTAL_IN0 is the input. Pulldown Reference clock input. LVCMOS/LVTTL interface levels. Pulldown MUX select pins. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q to go low and the inver ted output nQ to Pulldown go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pulldown Feedback divider select pins. Default /32. LVCMOS/LVTTL interface levels. Pullup Pulldown Reference clock output enable. Default Low. LVCMOS/LVTTL interface levels. Reference clock output. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP Rout Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor Output Impedance REF_OUT Test Conditions Minimum Typical 4 51 51 7 Maximum Units pF k k
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PRELIMINARY
TABLE 3A. COMMON CONFIGURATIONS TABLE
Input Reference Clock (MHz) 27 24.75 14.8351649 19.44 19.44 19.44 19.44 19.53125 25 25 25 25 25 26.5625 26.5625 26.5625 31.25 M Divider Value 22 24 40 32 32 32 32 32 25 25 24 24 24 24 24 24 18 N Divider Value 8 8 8 4 8 1 2 4 5 10 6 4 8 6 3 4 3 VCO (MHz) 594 594 593.4066 622.08 622.08 622.08 622.08 625 625 625 600 600 600 637.5 637.5 637.5 562.5 Output Frequency (MHz) 74.25 74.25 74.1758245 155.52 77.76 622.08 311.04 156.25 125 62.5 100 150 75 106.25 212.5 159.375 187.5 Application HDTV HDTV HDTV SONET SONET SONET SONET 10 GigE 1 GigE 1 GigE PCI Express SATA SATA Fibre Channel 1 4 Gig Fibre Channel 10 Gig Fibre Channel 12 Gig Ethernet
TABLE 3B. PROGRAMMABLE M DIVIDER FUNCTION TABLE
Inputs M2 0 0 0 0 1 1 M1 0 0 1 1 0 0 M0 0 1 0 1 0 1 M Divider Value 18 22 24 25 32 40 Input Frequency (MHz) Minimum 31.1 25.5 23.3 22.4 17.5 14.0 Maximum 38.9 31.8 29.2 28.0 (default) 21.9 17.5
TABLE 3C. PROGRAMMABLE N DIVIDER FUNCTION TABLE
Inputs N2 0 0 0 0 1 1 1 1 N1 0 0 1 1 0 0 1 1 N0 0 1 0 1 0 1 0 1 N Divide Value 1 2 3 4 (default) 5 6 8 10
TABLE 3D. BYPASS MODE FUNCTION TABLE
Inputs SEL1 0 0 1 1 SEL0 0 1 0 1 Reference XTAL0 XTAL1 REF_CLK REF_CLK PLL Mode Active (default) Active Active Bypass
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ICS844001-21 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Outputs, VO (LVCMOS) Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5V 10mA 15mA -0.5V to VDDO + 0.5V -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 82.3C/W (0 mps)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_LVDS = VDDO_CMOS = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO_LVDS, _CMOS IDD IDDA IDDO_LVDS, _CMOS Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 VDD - 0.15 3.135 Typical 3.3 3.3 3. 3 110 15 40 Maximum 3.465 VDD 3.465 Units V V V mA mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO_CMOS = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current REF_CLK, SEL0, SEL1, OE_REF, MR, M0, M1, N2 M2, N0, N1 REF_CLK, SEL0, SEL1, OE_REF, MR, M0, M1, N2 M2, N0, N1 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -5 Test Conditions Minimum Typical 2 -0.3 Maximum VDD + 0.3 0.8 150 5 Units V V A A A A V 0.5 V
IIL
Input Low Current
-150 VDD = 3.465V, VIN = 0V Output High Voltage; REF_OUT 2.6 VOH NOTE 1 Output Low Voltage: REF_OUT VOL Note 1 NOTE 1: Output terminated with 50 to VDDO _CMOS/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit Diagram".
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PRELIMINARY
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDO_LVDS = 3.3V5%, TA = 0C TO 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 400 50 1.5 50 Maximum Units mV mV V mV
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant crystal. 12 Test Conditions Minimum Typical Maximum 40 50 7 1 Units MHz MHz pF mW Fundamental
TABLE 6. AC CHARACTERISTICS, VDD = VDDO_LVDS = VDDO_CMOS = 3.3V5%, TA = 0C TO 70C
Symbol fOUT tPD tjit(O) tR / tF odc Parameter Output Frequency Propagation Delay, REF_CLK to NOTE 1 REF_OUT RMS Phase Jitter, (Random); NOTE 2, 3 Q, nQ Output Rise/Fall Time REF_OUT Output Duty Cycle Test Conditions Minimum 56 2.95 622.08MHz (12kHz - 20MHz) 20% to 80% 20% to 80% 0.92 300 300 50 50 Typical Maximum 700 Units MHz ns ps ps ps % %
Q, nQ REF_OUT NOTE 1: Measured from the VDD/2 of the input to VDDO_CMOS/2 of the output. NOTE 2: Phase jitter measured using a 25MHz quar tz crystal. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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PRELIMINARY
TYPICAL PHASE NOISE AT 622.08MHZ
OC-12 Filter
NOISE POWER dBc Hz
622.08MHz
RMS Phase Jitter (Random) 12kHz to 20MHz = 0.92ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding Sonet OC-12 Filter to raw data OFFSET FREQUENCY (HZ)
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PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
1.655% 1.655% VDD, VDDO_CMOS VDDA LVCMOS
nQx
SCOPE
3.3V5% POWER SUPPLY + Float GND -
SCOPE
Qx
VDD, VDDO_LVDS VDDA
Qx
LVDS
GND
-1.65V5%
3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
Phase Noise Mask
REF_CLK
VDD 2
f1
Offset Frequency
f2
VDDO_LVCMOS
REF_OUT
RMS Jitter = Area Under the Masked Phase Noise Plot
t
PD
2
RMS PHASE JITTER
PROPAGATION DELAY
80% Clock Outputs
80% VOD
80%
20%
80% 20%
20% tR tF
Clock Outputs
20% tR tF
LVDS OUTPUT RISE/FALL TIME
LVCMOS OUTPUT RISE/FALL TIME
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ICS844001AG-21 REV. A SEPTEMBER 14, 2007
ICS844001-21 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
VDD out DC Input
VDD out
LVDS
out
DC Input
LVDS
100
VOS/ VOS
out
VOD/ VOD
OFFSET VOLTAGE SETUP
DIFFERENTIAL OUTPUT VOLTAGE SETUP
nQ Q REF_OUT
V
DDO_CMOS
2
t PW
t
PERIOD
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
odc =
t PW t PERIOD
x 100%
LVDS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844001-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each VDDA.
3.3V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS:
CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. REF_CLK INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
OUTPUTS:
LVDS OUTPUT All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. LVCMOS OUTPUT All unused LVCMOS output can be left floating. There should be no trace attached.
CRYSTAL INPUT INTERFACE
The ICS844001-21 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN C1 22p X1 18pF Parallel Crystal XTAL_OUT C2 22p
FIGURE 2. CRYSTAL INPUt INTERFACE
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PRELIMINARY
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
VDD
R1 Ro Rs Zo = 50 .1uf XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER
TO
XTAL INPUT INTERFACE
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V 3.3V LVDS + R1 100
-
100 Ohm Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
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PRELIMINARY
SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS844001-21 application schematic. In this example, the device is operated at VDD = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 = 22pF and C2 = 22pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. One example of LVDS and one example of LVCMOS terminations are shown in this schematic. The decoupling capacitors should be located as close as possible to the power pin.
FIGURE 5. ICS844001-21 SCHEMATIC LAYOUT
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PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844001-21. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844001-21 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and LVDS Output Power Dissipation
*
Power (core, LVDS) = VDD_MAX * (IDD + IDDO_LVDS + IDDA ) = 3.465V * (110mA + 40mA + 15mA) = 572mW
LVCMOS Output Power Dissipation
* *
Output Impedance ROUT Power Dissipation due to Loading 50 to VDDO_CMOS/2 Output Current IOUT = VDDO_CMOS_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 7)] = 30.4mA Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 72 * (30.4mA)2 = 6.47mW per output
*
Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * frequency * (VDDO_CMOS)2 = 8pF * 25MHz * (3.465V)2 = 2.4 mW
Total Power Dissipation
*
Total Power = Power (core, LVDS) + Total Power (ROUT) + Total Power (125MHz) + Total Power (25MHz) = 572mW + 6.47mW + 2.4mW = 581mW
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PRELIMINARY
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 82.3C/W per Table 7 is: 70C + 0.581W * 82.3C/W = 118C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE JA FOR 24-TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 82.3C/W
1
78C/W
2.5
75.9C/W
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PRELIMINARY
RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 82.3C/W
1
78C/W
2.5
75.9C/W
TRANSISTOR COUNT
The transistor count for ICS844001-21 is: 4045
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PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
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PRELIMINARY
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS844001AG-21 ICS844001AG-21T ICS844001AG-21LF ICS844001AG-21LFT Marking ICS844001AG21 ICS844001AG21 TBD TBD Package 24 Lead TSSOP 24 Lead TSSOP 24 Lead "Lead Free" TSSOP 24 Lead "Lead Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Pats that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended termperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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PRELIMINARY
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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